In information theory, a low-density parity-check (LDPC) code is a linear error correcting code for use in transmission of a message over a, typically noisy, transmission channel. For example, LDPC codes are a powerful technique for forward error-correction (FEC). LDPC codes are finding increasing use in applications requiring reliable and highly-efficient information transfer over bandwidth or return channel-constrained links in the presence of corrupting noise. For example, at least partially due to the parallel structure of the LDPC decoders, LDPC decoders are well-suited for multi-gigabit communications. Disadvantageously, however, soft-decision LDPC decoders are typically relatively large, complex, and power-hungry circuits. For example, a 48 Gb/s LDPC decoder might consume 2.8 Watts and occupy more than 5 mm2 of chip area in 65 nm complementary metal-oxide-semiconductor (CMOS) technology. Accordingly, there is a need for LDPC decoders that support reliable and highly-efficient information transfer while consuming less power and occupying less chip area. Furthermore, and more generally, there is a need for improved minimum determination capabilities for use within various contexts.